Data is stored in an NVM cell by modulating the threshold voltage, Vth, of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) in the NVM through the injection of charge carriers into the charge-storage layer from the channel of the MOSFET. For example, with respect to a MOSFET, an accumulation of electrons in the floating gate, or in a dielectric layer above the FET channel region, causes the MOSFET to exhibit a relatively high Vth, while an accumulation of holes in the floating gate, or in a dielectric layer above the FET channel region, causes the MOSFET to exhibit a relatively low Vth. As illustrated in FIG. 1, the curves for source-to-drain current Ids versus the applied gate voltage Vg under the same drain voltage bias are parallel shifted toward the right along the applying gate voltage axis with higher threshold voltages and vice versa.
The number of bits stored in an NVM cell is determined by the number of resolvable threshold voltage levels, given by Number of Bits=log2 (number of resolvable threshold voltage levels). The more threshold voltage levels that can be sensed and resolved, the more bits that can be stored in a single NVM cell.
In the conventional MLC NVM, the threshold voltage level sensing has been done by comparing the current (voltage) responses from the memory cells with the current (voltage) response of reference cells, whose threshold voltage levels are pre-trimmed to the reference response current (voltage) levels under the same gate voltage bias. However, due to the non-uniformity of transconductance “gm” (where gm=ΔIds/ΔVg) and threshold voltage Vth for NVM cells inherited from the manufacturing process, the drive current-gate voltage curves are different in slopes (transconductance) and threshold voltages (onset point) for different NVM cells supposedly having the same threshold voltage as illustrated in FIG. 1. In FIG. 1, for each specified threshold voltage level, the solid-line represents the typical cell drive current vs. control gate voltage curve for a cell having the median transconductance, the dashed-line represents this curve for a cell having the maximum transconductance associated with this specified threshold voltage level, and the dotted-line represents this curve for a cell having the minimum transconductance with this specified threshold voltage level). Note that each line group (solid, dashed, dotted) for a specified threshold voltage level represents three different transconductances of the NVM cells. The four line groups shown vary their threshold voltages (ΔVth0, ΔVth1, ΔVth2, and ΔVth3) at four different threshold voltage levels. Specifically, in a population of NVM cells, the variations from cell to cell in aspect ratio (width/length) due to lithography, oxide thickness, or oxide trap density cause the variations in NVM cell transconductance, while the variations in channel impurities or fixed charges cause the variations in NVM cell original threshold voltages before programming. The variations among NVM cells including the reference cells impose a limitation on the number of resolvable threshold voltage levels capable of being achieved especially in the reference cell comparison scheme with a constant gate voltage applied as seen in FIG. 1.
Furthermore, since the memory cells experience more write-erase cycles than the reference cells, the transconductance degradation (smaller slope in the drive current-gate voltage curves) in memory cells become more severe than the transconductance degradation in reference cells. Throughout the device lifetime, other techniques to compensate this effect such as cycling the reference cells or re-adjusting the offsets of the sense amplifiers are required.
Other techniques to sense the drive current in NVM cells using stepped gate voltages to NVM cells have been applied to NOR-type NVM (M. Bauer et al., Intel Corporation, 2005 IEEE International Conference on Integrated Circuit and Technology) and to NAND-type NVM (T. S. June et al., Samsung Electronics, IEEE J. of Solid-State Circuit, Vol. 31, No. 11, pp. 1575, November 1996). In both these techniques, there is no requirement for the pre-trimmed reference cells. The stepped gate voltages are chosen in between specified threshold voltage levels. Besides including the whole threshold voltage distribution associated with a plurality of memory cells programmed to be at a specified threshold voltage level, the stepped voltage increment requires a guard-band voltage between the minimum (maximum) acceptable threshold voltage for a cell programmed to be at the specified level and the maximum (minimum) acceptable threshold voltage for a cell programmed to be at the next lower (higher) specified level such that the whole threshold voltage distributions of the programmed NVM cells for the levels after erase-write cycling and high temperature baking must still reside between the stepped gate voltages as illustrated in FIG. 2 (solid-line original and dotted-line worn). With large enough gate voltage increments to the control gates of NVM cells, combination logic circuitry receiving the responses of sense circuitry can determine the threshold voltage levels of the NVM cells after applying all three stepped voltages and thus determine the binary information represented by the charges stored on the memory cell.
As seen in the stepped gate voltage schemes as illustrated by FIG. 2, the resolvable levels for the MLC NVM are limited by the distribution of the programmed NVM threshold voltages and the guard-band voltages between levels. The width of the threshold voltage distribution associated with the MLC NVM cells for each threshold voltage level depends on the uniformity of programming conditions (speed, background coupling, and noise) and the characteristics of the NVM cells. It has been reported that the distribution of programmed threshold voltages for an NAND-type flash memory is widened by cell program speed, background pattern dependency, read-verification offset, and neighboring floating gate coupling (T. H. Cho et al., Samsung Electronics, IEEE J. of Solid-State Circuit, Vol. 36, No. 11, pp. 1700, November 2001). The widened distribution of threshold voltage after erase-write cycling and high temperature baking (as shown in FIG. 2 by the dotted line curves) strongly depends on the gate dielectric thickness and quality of the NVM cells. These parameters can vary with the NVM cells in a given memory as well as with the NVM cells from memory to memory. Thus FIG. 2 shows in solid lines the distributions of actual threshold voltages associated with four different given threshold voltage levels when the NVM cells are relatively new and have been programmed only a few times and also shows in dotted lines the same distributions after the NVM cells have been used for some time and reprogrammed a large number of times. The dotted line distributions show that with use, the threshold voltages of the NVM cells shift down. To determine the particular threshold voltage associated with a given NVM cell, stepped gate voltages are applied to the control gate of the cell and the drive current Ids is measured. The two stepped gate voltages which result in no Ids current and an Ids current allows a sense amp together with logic circuitry to detect the actual threshold voltage level of the NVM cell and thus the binary information stored in the cell.
In order to ensure that the threshold voltage of some cells in the NVM cell array do not, with age, have a threshold voltage which falls below the lower of the stepped gate voltage for a given reference threshold voltage, a guard band is provided between what is expected to be the lowest threshold voltage for an NVM cell in the memory array and the stepped gate voltage directly below that given reference threshold voltage. A similar guard band is provided between the highest expected threshold voltage associated with a given threshold voltage level and the stepped gate voltage directly above this given threshold voltage level to ensure that no NVM cell in a memory array has an actual threshold voltage which, when the cell is being programmed to the given threshold voltage, exceeds this next higher stepped gate voltage. FIG. 2 shows these guard band voltages in relation to the stepped gate voltages for a typical array of NVM cells.